1. Field of the Invention
This invention relates generally to the field of semiconductor processing and more specifically to oxide deposition during semiconductor fabrication.
2. Background of the Invention
Semiconductor integrated circuits (ICs) are typically fabricated by successively forming patterned layers on a top surface of a semiconductor wafer. The wafer is typically silicon, while each layer is composed of metals or insulators. Each layer is patterned by lithographic and etching techniques that are suitable for the layer material. A layer formed by metal is typically separated from another metal layer by an insulation layer such as oxide. Depending on the level of complexity, an IC will require from 5 to 18 different masks (i.e., "work plates") to create the layers of circuit patterns that must be formed on the surface of a silicon wafer. To begin the fabrication process, a silicon wafer is loaded into a 1200 Celsius furnace in which oxygen flows. As a result, a layer of silicon dioxide is "grown" on the surface of the wafer.
The oxidized wafer is then coated with a light-sensitive, honey-like emulsion known as a photoresist. Negative photoresist hardens when exposed to ultra-violet light. Suitable materials for the photoresist include materials that comprise novolac resin and a photo-active dissolution inhibitor. Other suitable materials may be used as a photoresist as known to those skilled in the art. The photoresist may have any suitable thickness, and is disposed by use of, for example, the spin coating method.
An appropriate glass mask is placed directly over the wafer to transfer the first layer of circuit pattern onto the wafer. During the photolithographic process, the mask is aligned relative to the wafer by use of a lithography system that typically includes subsystems such as a precision alignment system, a reticle alignment system, and an illumination system. An ultra-violet light is then projected through the mask, and the dark patterns on the mask conceal wafer areas that are aligned with the dark patterns. The photoresist areas (which are aligned with the dark mask patterns) do not receive the ultraviolet light and therefore remain soft. In contrast, the light hardens the other photoresist areas that receive the ultra-violet light passing through the mask.
The wafer is then washed in a solvent that removes the soft photoresist, but leaves the hardened photoresist on the wafer. The oxide layer is exposed in the areas in which the photoresist was removed. An etching bath then removes the exposed oxide areas and the remaining photoresist. The result is a stencil of the mask patterns, formed by minute channels of oxide and silicon. The wafer is then placed in a diffusion furnace for impurity doping whereby dopant atoms enter the areas of exposed silicon, forming a pattern of, for example, n-type material. An etching bath removes the remaining oxide and a new layer of silicon is deposited onto the wafer. Thus, the first layer of the chip is completed, and the masking process described above is repeated for the next mask.
Alignment marks are used to align a mask with a wafer. At least two alignment marks are required for global alignment that measures the position and orientation of the wafer. Alignment marks, known particularly as chip marks, are also required to determine shift, rotation, magnification, and trapezoidal corrections for each chip, and to correct for the placement of individual circuit patterns on the wafer.
However, alignment marks can be affected during the semiconductor fabrication process, thereby leading to misalignment between the mask and the entire wafer. For example, during shallow trench isolation (STI) an extra oxide deposition step is used to fill the shallow trenches between active areas of the wafer. This extra oxide deposition step is followed by chemical mechanical polishing that may adversely affect the wafer alignment marks.
As another example, during an oxide deposition step, an oxide layer typically forms over the alignment marks. Since the oxide layer may be transparent, the alignment marks may be visible to the alignment system. However, one problem is that certain thickness ranges of the oxide layer will cause destructive interference of the alignment beam from the alignment system whereby the alignment beam will cancel itself out as the beam reflects back from the alignment mark area to the alignment system. This destructive interference of the alignment beam may erroneously give a reading of precise alignment between the mask and the wafer when in fact there is misalignment.
Thus, there is a need for an apparatus and method for preserving alignment marks during the semiconductor fabrication process. What is further needed is an apparatus and method that prevent oxide deposition upon the alignment marks so that destructive interference of the alignment beam is prevented.